A Verification Platform for System on Chip

System on Chip technology will reshape common design practice. The pressure to create a working System on Chip design as early as possible leads designers to consider using a platform based design method, called a system integration platform. In this design methodology, a system is built from intellectual property blocks in a plug and play environment. By using this approach, designing an application is a matter of selecting from a set of standard components with compatible specifications. Subsequently, a similar platform can be constructed for formal verification. Every component in the integration platform has a corresponding formal model in the formal platform. This dissertation proposes a methodology to develop formal models of System on Chip design and to verify the design from a system level point of view. The methodology is based on two components: a formal verification environment and a formal verification platform. A formal verification environment is an environment where a selection of formal tools are integrated to offer a complete set of formal verification techniques. It combines the capabilities of the HOL98 theorem prover, the ACL2 theorem prover, and the SMV model checker. A formal verification platform is a standardised platform where formal models can be integrated and system level validation of the design can be performed. In the verification platform, all formal models are formalised in the most suitable formalism. They are connected using higher order logic as the glue logic. The formal verification platform provides an environment to analyse the combined properties of the design. Two formal verification platforms were formalised to demonstrate the application of a formal verification environment in system level verification. In the first platform, a complete system was formalised. The verification efforts were targeted to verify whether properties of the system as a whole satisfied the specifications. The verification showed that the system had liveness properties and that all master requests will eventually be granted by the arbiter. The software was also verified to ensure that it was correctly executed. In the second platform, a partial system is defined. Applications were developed by integrating additional components onto the platform. The formal verification platform was used to obtain specific properties of the system. These properties can be used as the guidelines for tighter specifications in the selection of components.